Fail Safe General Purpose Digital Interface (GPDI)
92. Diagram 18 shows the circuit that is used to integrate analog signal voltages that come from the outside world into signal processors and component controllers that are used in the Heat Engine environment.
93. From the vantage point of the outside world, the circuit has exactly one analog input and one analog output.
94. The circuit is designed such that it will:
A. Pass an analog input signal as a digital data word from it's analog input to the data bus of the component controller in which it is integrated.
B. Pass a digital word from it's component controller data bus as an analog signal to it's analog output.
C. Pass an analog signal from it's analog input directly to it's analog output, whereby the the component controller to which it is connected can read the value that is being passed from the analog input to the analog output as a digital word.
D. Pass a modified analog signal that is digitized at it's analog input to it's analog output. Whereby, the component controller can cause a value to be added or subtracted from the original input value so that the output analog voltage will be modified by the amount specified by the component controller. This function allows values calculated by the component controller to be joined together with human inputs values so that the component controller can modify the analog values that are passed from the analog input to the analog output within given ranges, without completely overriding human control values in one or more steps that all occur outside the tracking capability of the said humans.
Example: If the value at the analog input is the brake pedal voltage of an electric vehicle, the component controller can add a value to the output analog value, whether or not a value exist at the said analog input.
Example: If the value at the analog input is a gas pedal voltage of an electric vehicle, the component controller can subtract a value from or add a value to the voltage at the output of the circuit.
Example: If the value at the analog input is a gear lever position value, the component controller will usually not be required to add or subtract any values from the said analog input, unless that input voltage does not match the selected position of that voltage input interface, whereby the component controller will usually switch the gear lever position voltage down towards zero in an orderly fashion.
E. The registers REG 1,2,3 works together with the multiplexer (MUX) and the tri-state (TS) bus drivers to:
I. Pass the digitized input analog values to the CPU in the component controller.
II. Pass the re-digitized analog output value back to the component controller so that it will definitely know which value is at it's output.
III. Pass the control word that the component controller uses to control the GPID back to itself so that it can check, if the said control value is correct.
General purpose Digital Interface Name Key
ANALOG IN - This signal is any analog input signal that is coming from the outside world.
ANALOG OUT - This analog output signal is in the first instance, defined to be exactly the same as the signal at the ANALOG IN signal, but it can be modified. It can also be an analog signal that is generated solely by the component controller when a ANALOG IN value does not exist.
A/D 1 - This is an Analog/Digital converter that converts an incoming signal to a digital value that can also be passed on to a CPU.
ALU - This is an Arithmetic Logic Unit that can be instructed to:
A. Add the value at input (B) to the value at input (A).
B. Subtract the value at input (B) from the value at input (A).
C. Let the value at input (A) pass through without modifying it in any way.
U/D CNTR - This is an Up/Down (U/D) counter that is loaded with the value that exists at the output of the Arithmetic Logic Unit (ALU). In the first instance it will act as an holding register for values at it's input. It will also count up to a maximum value or down to zero. It does not repeat, unless it is reloaded. It's Hold (HLD) input can be connected through the OR gate shown in the circuit to the Timer Relay Signal (TRS) that comes from a component controller or Main Signal Processor (MSP) so that if the said TRS signal goes to zero, the counter will leave the Hold state and either count down to zero or up to a maximum, depending on the state that exists at it's U/D input. The other side of the OR gate is connect through REG1 to the Data Bus of the Component Controller so that it can control the activity of the counter when the Timer Relay Signal (TRS) is correct.
DIV X - This is a frequency divider that is used to divide the clock frequency of the U/D CNTR down to a suitable frequency so that, when required, the rise and fall times of the output voltage ANALOG OUT can be adjusted to suit individual requirements.
D/A 1 - This is the output Digital/Analog converter that converts the values passed to it from the U/D CNTR to an analog value and passes it on to an outside world destination.
A/D 2 - This Analog/Digital converter is used to convert the ANALOG OUT signal back to a digital signal that is passed back to the component controller so that it can check and see, if the correct analog values are at the D/A 1 output.
CC1, CC2 - These two Conversion Complete signals are used to load the output values of the associated converter into the associated register REG2 and REG3. When required, they are also used to inform the component controller through it's INT1 and INT2 interrupt lines when new data is available in the said registers.
REG 1 - This register is used to control the function of the ALU, U/D CNTR and DIV X components. In stand alone applications when the Data Bus is not used, the inputs to this register can be set according, so that the circuit only exhibits one function that affect the way the ANALOG IN signal is treated, before it reaches the ANALOG OUT.
REG 2,3 - These registers are used to hold data so that the component controller can read them.
MUX + TS - This circuit combination allows the Component Controller to read the data in the registers REG 1,2,3. The Read/Write (R/W) and Address Lines (AD) are connected to the Multiplexer (MUX) and Tri-State (TS) circuit combination. The output of MUX is connected to the Tri-State (TS) bus drivers.
DI1 - Comes from the output of REG1 and is connected to input 1 of the multiplexer (MUX).
DI2 - Comes from the output of A/D 1 and is connected to the input of REG2. The output of REG2 is connected to input 2 of the multiplexer (MUX).
DI3 - Comes from the output of A/D 2 and is connected to the input of REG3. The output of REG3 is connected to input 3 of the multiplexer (MUX).
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Diagram 18
Page 7
This General Purpose Digital Interface circuit is used to pass data
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