Data Link Controller
79. Diagram 15b shows the function blocks of the Link Data Link Controllers that only implement serial links between Component Controllers and or the Main Signal Processor.
Example: This DLC groups the serial data from Component Controllers and pass them on to the Main Signal Processor. There are used through out the Heat Engine when real world component layout require line drivers between connections. For example, in the Bucket Chain Heat Engine, the Front End (HEFE), Intermediate (HEIS) and Back End (HEBE) sections of that engine each contain one. That allows the number of serial connections between Component Controllers and the Main Signal Processor to be reduced, without sacrificing error detection and correction capability, because the Data Link Controllers are able to check the validity of the data that they read from their memory and inform the Main Signal Processor as well as pass zero turn off signals to the component controllers to which they are connected. In reference to the Data Link Controller program execution memory, Read Only Memory (ROM) can withstand higher over voltages than Random Access Memory (RAM).
80. If for example, in the case of the electric vehicles, one of the serial connections to the Main Signal Processor breaks, it will know that it has not received any data from a specific DLC within the specified cycle time and abort updates to the Timer Relays, which will cause power to be removed from the electric motors.
81. The action of Data Link Controllers are controlled by Sequencers in coordination with their built in timers. The Sequencers are required in order to generate instruction branches and the timers are required in order to define cycle times.
CPU to outside world communication interface structure
It's position in computing hardware bus structure circuitry is shown in Diagram 13 and Diagram 14.