E-Clutch + E-Brake Control (E-C-E-B)

127. Diagram 20a shows a detailed (DE-C-E-B ) view of the E-C-E-B circuit block shown in Diagram 20. The ZCD signal is used to generate and synchronize the Electronic Clutch (E-C) and Electronic Brake (E-B) signals to the UVW voltage that supplies the electric motors. The graphical representation of those signals are shown in Diagram 20b. The C2W and C4W signals are used to enable the E-C and E-B signals inside the Clutch + Brake Power (CBP) circuit block, so that apart from the information over the Serial Link (SL) about which type of drive combination is selected by IG2W and or IG4W in the E2W/4WDS circuit block that is in the Man Machine Interface (MMI). The synchronized versions C2W and C4W are also available to the Clutch + Brake Power (CBP)  circuit.

128. The electric vehicle drive being described here does not contain any mechanical gears or transmission.
Diagram 20a shows a detailed view of how the E-Clutch (E-C) and E-Brake (E-B) signals are generated and Diagram 20b, show the basic pulse diagram that is referenced to the ZCD signal of the UVW voltage.

How Detailed (DE-C-E-B) Works -
Diagram 20a:

DE-C-E-B Name Key
CMP-CTRL       Component Controller.

ZCD                   Zero Crossing Detector Circuit.

Ignition            Part of the reset function

NU1                 Neutral State of the Gear Lever. Part of the reset function.

CP1/CP2         Clutch Pedal voltage from the Man Machine Interface (MMI).

CP3                  Same as CP1/CP2, if the component controller CMP-CTRL does not modify it. It can be used to drive the electric clutch in the Clutch + Brake Power (CBP) circuit, if CP1 or CP2 is not used there instead.

BP1/BP2           Brake Pedal voltage from the Man Machine Interface (MMI).

BP3                    Same as BP1/BP2, if the component controller CMP-CTRL does not modify it. It can be used to drive the electric brake in the Clutch + Brake Power (CBP) circuit, if BP1 or BP2 is not used there instead.   

EBC                   Confirmation signal from the Component Controller (CMP-CTRL) that E-Brake is being applied. This activation instruction could very well originate at the Main Signal Processor, because the vehicle needs to avoid an obstacle or is traveling on a slope at a speed that has not yet inserted enough kinetic energy into the body of the said vehicle, which is the same as saying it can be used to avoid roll back.

EGC                  Confirmation from the Component Controller (CMP-CTRL) that the Gas Pedal (GP1) voltage is above zero and E-B is not required, unless EBC is used to  activate it.

DIV 256            Counter

FF1                    Flip Flop

SREG, EREG    Data Registers

SCMP, ECMP   Digital comparators.

ENREG            Indicates that the Address Lines (AD) are used to select registers.

LDREG            Indicates that the R/W line is used to load registers. 
C1             The output of this comparator will be HIGH when any phase of the UVW three phase voltage is above zero. The signal allows clutch pulses to be placed on the E-Clutch (E-C) line when the other signals are also correct.

C2,C3,C4   These three comparators ensure that clutch pulses are available for each individual phase of the UVW voltage. If one of the phases drop out, the pulses for that phase will also drop out and the E-Clutch (E-C) will be turned off for that phase. The E-Brake (E-C) will be available. That means that in such a case the vehicle will be moving in an on/off way, because if the E-C pulses are missing, the UVW voltage will also be off.

Vehicle Start Up Clutch is ON, Therefore CP1/CP2 is high:
A. Each time one of the phases goes positive,  C2,C3 or C4 will cause the DIV 256 counter and the Flip Flop  (FF1) to be cleared, which causes the clutch pulses to be synchronized with the UVW voltage.

B. The DIV 256 counter will count up to the value that was previously placed in the register SREG by the component controller. At that point the digital comparator SCMP will set Flip Flop (FF1)  and it's Q output is E-Clutch (E-C), which is the clutch power ON/OFF signal.

C. When the DIV 256 counter reaches the value placed in the register EREG, the output of the digital comparator ECMP will turn off the Flip  Flop (FF1) and clear the DIV 256 counter.

D. The DIV 256 counter will start counting up again to the value in the register SREG and the cycle begins again.

E. The E-C signal pulses means that no gears are required in the electric vehicle drive transmission being described in this text. The drive motors will automatically receive more power as the rotor speed differs from the speed of the rotating stator magnetic field. There are resistors in the rotor circuit of the electric motor that will limit the maximum current for each speed range set by  the Gear Lever (GL).

C5,C6,C7   These three comparators are used to synchronize the position of the E-Brake (E-B) pulses to the Zero Crossing Detect (ZCD) signal. The E-Brake (E-B) signal is the inverted Q signal from FF1, so that it will only be active when E-C is OFF. The circuit is designed such that the BP1/BP2 voltage that comes through the General Purpose Interface (GPDIs  - GPD1..GPD4) from the Man Machine Interface (MMI) to these components will override the E-Brake (E-B ) function when a driver is using the Brake Pedal. That means that the E-Brake function can be used by the Main Signal Processor (MSP) to force a vehicle to avoid obstacles, depending on the information that it receives from other sensors such as steering wheel position and Distance Controller circuit. The sensors described in other parts of this text have reaction times that are several thousand times faster than a human. That means that Electric Drive functions will be controlled by timers so that they are related to the vehicle and not software speed or data conversion times.

How To Guess The Control Data Sequence Time:

Example: Assume that the frequency of the electric motors will be 50Hz.
Y = Hardware Time.
N = Number of clocks for a Read/Write access
D = Defined number of Read/Write Access for one real data movement
W = Width of one Data Bus clock
P = Component Controller Time
X = Number of available data move instruction cycles
Y = 1/50Hz = 20ms
N = 4
D = 8
W = 20e-9s
P = N * D * W = 4 * 8 * 20e-9 = 6,4E-7s
X = Y/P = 31250  Real Data moves in 20ms

Note: The Data Link Controller in a Component Controller requires the most time in order to move a data word and that is the longest signal propagation delay that will be of relevance on the digital level. It is assumed that it will require a maximum of 8 read or write steps in order to execute a transaction. That is more than is stated in the section Data Link Controller Fail Safe Read/Write above, but this is safe side logical guessing. The other reason is that, depending on the type of memory use, wait states may be required. If there is a problem, a faster Data Link Controller hardware can be used.
It can be seen from the drawings that neither the Main Signal Processor nor a  Component Controller will be required to move 31250 data words in 20ms.

In comparison with moving picture type systems, note how the numbers match, which is good when the electric current generator is to be synchronized with a public power supply. It is said that moving picture systems were synchronized to the public power supply system, before quartz were available.
It can also be seen that fail safe digital data applications are slower than what is considered to be normal visual data applications, but they are still fast enough for all relative mechanical applications, which is where fail safe functions are required. It can hereby be noted that 31250 data words is in fact a frequency that is 1.3 times above that of most normal mechanical gears.

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