Data Link Controller Fail Safe Read/Write
78. Diagram 15 shows the data bus arbitration logic that is used to implement data transactions by the Data Link Controller (DLC). The circuit is expandable from one bit to any data bus width.
Data Link Controller Fail Safe Read/Write - Name Key
DLCDB Data Link Controller Data Bus. This is the data bus along which data is moved, when it is moved from a source to a new destination. It is not necessarily the data bus that carries program code.CPUDB CPU Data Bus that is external. The Data Link Controller (DLC) can contain an address sequencer that vectors and jumps to instruction sequences or a standard CPU that does the same thing.
SLPDB Serial Data Bus. This is the data that the Data Link Controller DLC) uses to move data between itself and the outside world. The serial connections are classified here as being part of the outside world.
A,B,C,D,E,F,G,H,I, J Bus Arbitration Logic Control Inputs. They are controlled by the data that the address sequencer reads from the program memory that is not shown in the drawing. In the simplest form the sequencer can use two of it's main clock cycles to change the state of these control data lines. One to read the required data from memory and store it in a register, whose outputs are shown in the drawing and the second is used to allow the states on these control lines to take effect within the circuit.
IT1, IT2 Interrupt lines to the Data Link Controller (DLC) control logic.
R1,R2 Data registers. They are used as intermediate storage for data that is being moved.
C1,C2 Binary Comparators. They are used to compare two data words in order to see if they are not equal.
T Tri-State Bus Drivers.
How It Works:
Write From SLPDB to DLCDB Data Bus:
A B C D E F G H I J
0 0 0 0 1 0 0 0 0 0 When serial data is received it will be at the parallel output of an internal shift register that is connected to the SLDB data bus, therefore this signal line is used to place that data onto the DLC data bus so that it can be written to DLC Memory. In fact data that is coming from any part of the outside world is passed on to the system via the SLDB data bus by setting this data bus arbiter control combination.
Write From DLCDB To External SLPDB or CPUDB Data Busses:
When the DLC needs to read data from the DLC Memory to the CPUDB or SLPDB Data Bus, it does the following:
A B C D E F G H I J
1 1 0 0 0 0 1 0 0 0 It reads the data word from DLC Memory along the DLCDB data bus and writes it in the register R1. The output of R1 is inverted.
A B C D E F G H I J
0 0 1 0 0 0 1 0 0 0 It writes the inverted data at the output of R1 back to the same address in DLC Memory.
A B C D E F G H I J
1 0 0 1 0 0 1 0 0 0 It reads the same data word, which in fact is now inverted, from DLC Memory to the input of register R1. At the same time the Comparator C1 is enabled and it's output IT1 will show a logical HIGH, if the word at the output of R1 does not match the word that is on the DLCDB data lines. In such a case, the controller will terminate the read cycle and report a memory read error.
A B C D E F G H I J
1 1 0 1 0 0 1 0 0 0 If the data word is correct, it will be loaded into register R1, whereby the data word is inverted back to it's original value.
A B C D E F G H I J
0 0 1 0 0 0 1 0 0 0 It writes the inverted data at the output of R1, which is in fact the correct data word, to the same address in DLC Memory. After that, one or both of the next two instruction cycles can be executed.
A B C D E F G H I J
0 0 0 0 0 1 1 0 0 0 It places the data at the output of R1 on to the SLDB data bus. The real data destination can be a shift register or something else that is connected to the said data bus.
OR
A B C D E F G H I J
0 0 0 0 0 0 1 0 0 1 It writes the data at the output of R1 to the external CPUDB Memory.
Write From External CPUDB to DLCDB:
When the DLC needs to read data from the external CPUDB Memory to DLCDB Memory it does the following:
A B C D E F G H I J
1 1 0 0 0 0 0 1 0 0 It reads the data word from CPUDB Memory and writes it in to register R2.
A B C D E F G H I J
0 0 1 0 0 0 0 1 0 0 It writes the inverted data at the output of R2 back to the same address in CPUDB Memory.
A B C D E F G H I J
1 0 0 1 0 0 0 1 0 0 It reads the same data word, which in fact, is now inverted, from CPUDB Memory to the input of register R2. At the same time the Comparator C2 is enabled and it's IT2 output will show a logical HIGH, if the word at the output of R2 does not match the word that is on the CPUDB data lines. In such a case, the controller will terminate the read cycle and report a memory read error.
A B C D E F G H I J
1 1 0 1 0 0 0 1 0 0 If the data word is correct, it will be loaded into register R2, whereby the data word is inverted back to it's original value.
A B C D E F G H I J
0 0 1 0 0 0 0 1 0 0 It writes the inverted data at the output of R2, which is in fact the correct data word, to the same address in CPUDB Memory.
A B C D E F G H I J
0 0 0 0 0 0 0 1 1 0 It writes the data at the output of R2 to the external DLCDB Memory.
OR
A B C D E F G H I J
0 0 0 0 0 0 0 1 0 1 It writes the data at the output of R2 to something on the SLDB data bus. This would be an emergency short cycle function, because the DLCDB Memory is not used. This can be done, because the Data Link Controller (DLC) can interpret the meaning of a data word according to Identification, Instruction and Data while it is being read as shown in Diagram 13. This is possible, if the Program Execution Bus of the Data Link Controller is not the same as the one on which data that is to be manipulated is moved. For example, if the DLCDB Memory becomes defective, it can be by passed. This capability is useful in circumstances where total system shut down by the Main Signal Processor is not the most suitable reaction to a memory or serial link error. Vice versa, some Component Controllers can be given enough software and sensor capability so that they can continue with their part of the regulation work, even if the serial communication with the Main Signal Processor has broken down. That means that Component Controllers can be built as Main Signal Processors so that they can get and use the same data that is relevant to them from the outside world as well as from the said Main Signal Processor. In the case of a damaged Main Signal Processor, a short distance radio link can be used by the Component Controllers to pass on relevant information to other Component Controllers, whereby one of the functioning Component Controllers can be designated to be the Main Signal Processor. This strategy allows decisions to be made about the validity of incoming signals, before the decisions about the appropriate reaction to those signals are made.
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Diagram 15
Page 3
Computer memory fail safe read/Write hardware circuit
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